CMOS：混合信号电路设计

Chapter 30 Data Converter Modeling

30.1 Sampling and Aliasing: A Modeling Approach

30.1.1 Impulse Sampling A Note Concerning the AAF and RCF Time-Domain Description of Peconstruction Using SPICE for Spectral Analysis (Looking at the Spectrum of a Signal) Representing the Impulse Sampler's Output in the Z-Domain

30.1.2 The Sample and Hold SPICE Modeling the Sample and Hold S/H Spectral Response Circuit Concerns for Implementing the S/H

30.2 SPICE Models for DACs and ADCs

30.2.1 The Ideal DAC SPICE Modeling Approach

30.2.2 The Ideal ADC Summary

30.3 Quantization Noise.

30.3.1 Viewing the Quantization Noise Spectrum Using Simulations An Important Note RMS Quantization Noise Voltage Treating Quantization Noise as a Random Variable Calculating RMS Quantization Noise Voltage from a Spectrum The DFT's Relationship to the ...

30.3.2 Quantization Noise Voltage Spectral ensity

Reducing Quantization Noise Using Averaging The Noise Spectral Density View of Averaging An Important Note Practical Implementation of raging in ADCshapter 31 Data Converter SNR

31.1 Data Converter SNR: An Overview

31.1.1 Effective Number of Bits Signal-to-Noise Plus Distortion Ratio Spurious-Free Dynamic Range

Dynamic Range Specifying SNR and SNDR

31.1.2 Clock Jitter Using Oversampling to Reduce Sampling Clock Jitter Stability Requirements A Practical Note Modeling Clock Jitter with SPICE

Using Our SPICE Jitter Model

31.1.3 A Tool: The Spectral Density The Spectral Density of Deterministic Signals: An Overview The Spectral Density of Random Signals: An Overview Phase Noise from Measured Data

31.2 Improving SNR Using Averaging

31.2.1 Using Averaging to Improve SNR Spectral Density View of Averaging Revisited An Important Observation Jitter and Averaging Relaxed Requirements Placed on the Antialiasing Filter Data Converter Linearity Requirements Adding a Noise Dither to the A...

31.2.2 Decimating Filters for ADCs

The Accumulate and Dump

Averaging without Decimation

Relaxed Requirements Placed on the ntialiasing Filter Revisited mplementing Averaging Filters Aliasing Concerns When Using Decimation A Note Concerning Stability Decimating Down to 2B

31.2.3 Interpolating Filters for DACs

The Dump and Interpolate

Practical Implementation of terpolators

31.2.4 Bandpass and Highpass Sinc Filters Canceling Zeroes to Create Highpass and Bandpass Filters Frequency Sampling Filters

31.3 Using Feedback to Improve SNR

31.3.1 The Discrete Analog Integrator A Note Concerning Block Diagrams

31.3.2 Modulators Chapter

32 Noise-Shaping Data Converters

32.1 Noise-Shaping Fundamentals.

32.1.1 SPICE Models Nonoverlapping Clock Generation and Switches Op-Amp Modeling SPICE Modeling a 1-Bit ADC

32.1.2 First-Order Noise-Shaping A Digital First-Order NS Demodulator Modulation Noise in First-Order NS Modulators RMS Quantization Noise in a First-Order Modulator Decimating and Filtering the Output of a NS Modulator Implementing the Sinc Averaging ...

Op-Amp Gain (Integrator Leakage)

Op-Amp Settling Time

Op-Amp Offset

Op-Amp Input Referred Noise Practical Implementation of the First-Order NS Modulator FullyDifferential Modulator with a Single-Ended Input

32.1.3 Second-Order NoiseShaping

Second-Order Modulator Topology

Integrator Gain Implementing Feedback Gains in the DAI Using Two Delaying Integrators to Implement the Second-Order Modulator Selecting Modulator (Integrator) Gains Understanding Modulator SNR

32.2 Noise-Shaping Topologies

32.2.1 Higher-Order Modulators M'h-Order Modulator Topology Decimating the Output of an Mth-Order NS Modulator Implementing Higher-Order, Single-Stage, Modulators

32.2.2 Multibit Modulators Simulating a Multibit NS Modulator Using SPICE Multibit Demodulator sed in a NS DAC) Implementation (Error Feedback) Implementation Concerns

32.2.3 Cascaded Modulators Second-Order (1-1) Modulators Third-Order (1-1-1) Modulators

Third-Order (2-1) Modulators Implementing the Additional Summing Input

32.2.4 Bandpass Modulators Implementing a Bandpass Modulator Shapter 33 Submicron CMOS Circuit Design 2

33.1 Submicron CMOS: Overview and Models

33.1.1 CMOS Process Flow

33.1.2 Capacitors and Resistors

Using a MOSFET as a Capacitor

Using a Native or Natural MOSFET acitor

The Floating MOS Capacitor

Metal Capacitors

An Important Note

Resistors

33.1.3 SPICE MOSFET Modeling

Model Selection

Model Parameters

An Important Note

A Note Concerning Long L MOSFETs

33.2 Digital Circuit Design

33.2.1 The MOSFET Switch

Bidirectional Switches

A Clocked Comparator

Common-Mode Noise Elimination

33.2.2 Delay Elements

33.2.3 An Adder

33.3 Analog Circuit Design.

33.3.1 Biasing

Selecting the Excess Gate Voltage

Selecting the Channel Length

Small-Signal Transconductance, gm

MOSFET Transition Frequency, fT

The Beta Multiplier Self-Biased Reference

33.3.20p-Amp Design

Output Swing

Slew-rate Concerns

Differential Output Op-Amp

33.3.3 Circuit Noise

Thermal Noise

The Spectral Characteristics of Thermal Noise

Noise Equivalent Bandwidth

MOSFET Noise

Noise Performance of the Source-Follower

Noise Performance of a Cascade of Amplifiers

DAI Noise Performance Chapter

34 Implementing Data Converters

34.1 R-2R Topologies for DACs

34.1.1 The Current-Mode R-2R DAC

34.1.2 The Voltage-Mode R-2R DAC

34.1.3 A Wide-Swing Current-Mode R-2R DAC

DNL Analysis

INL Analysis

Switches

Experimental Results

Improving DNL (Segmentation)

Trimming DAC Offset

Trimming DAC Gain

Improving INL by Calibration

34.1.4 Topologies Without an Op-Amp

The Voltage-Mode DAC

Two Important Notes Concerning Glitches

The Current-Mode (Current Steering) DAC

34.20p-Amps in Data Converters.

Gain Bandwidth Product of the Noninverting Op-Amp Topology

Gain Bandwidth Product of the Inverting Op-Amp Topology

34.2.10p-Amp Gain

34.2.20p-Amp Unity Gain Frequency

34.2.30p-Amp Offset

Adding an Auxiliary Input Port

34.3 Implementing ADCs

34.3.1 Implementing the S/H

A Single-Ended to Differential Output S/H

34.3.2 The Cyclic ADC

Comparator Placement

Implementing Subtraction in the S/H

Understanding Output Swing

34.3.3 The Pipeline ADC

Using 1.5 Bits/Stage

Capacitor Error Averaging

Comparator Placement

Clock Generation

Offsets and Alternative Design Topologies

Dynamic CMFB

Layout of Pipelined ADCs hapter

35 Integrator-Based CMOS Filters

35.1 Integrator Building Blocks

35.1.1 Lowpass Filters

35.1.2 Active-RC Integrators

Effects of Finite Op-Amp Gain Bandwidth Product Active-RC SNR

35.1.3 MOSFET-C Integrators

Why use an Active Circuit (an Op-Amp)

35.1.4 gm-C (Transconductor-C) Integrators

Common-Mode Feedback Considerations

A High-Frequency Transconductor

35.1.5 Discrete-Time Integrators

An important Note

Exact Frequency Response of a First-Order Discrete- Time

Digital (or Ideal SC) Filter

35.2 Filtering Topologies.

35.2.1 The Bilinear Transfer Function

Active-RC Implementation

Transconductor-C Implementation

Switched-Capacitor Implementation

Digital Filter implementation

The Canonic Form (or Standard Form) of a Digital Filter

35.2.2 The Biquadratic Transfer Function

Active-RC Implementation

Switched-Capacitor Implementation

High Q

Q Peaking and Instability

Transconductor-C Implementation

The Digital Biquad

35.3 Filters using Noise-Shaping.

Removing Modulation Noise

Implementing the Multipliers

Chapter 36 At the Bench

36.1 A Push-Pull Amplifier

Deadbug Prototyping

Probing

Testing the Circuit

36.2 A First-Order Noise-Shaping Modulator

Prototyping the Modulator

36.3 Measuring 1/f Noise

MOSFET Noise

Input-Referred Noise Voltage

Chopper Stabilization

36.4 A Discrete Analog Integrator

Clock Generation

Prototyping the Filter

36.5 Quantization Noise

Prototyping the ADC Circuit

Index

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