PCI-X System Architecture（影印版）

About This Book

The MindShare Architecture Series

Cautionary Note

This Book Assumes PCI Background Knowledge

Specifications This Book Is Based On

Organization of This Book

Who This Book Is For

Prerequisite Knowledge

Documentation Conventions

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Part l: Basic Concepts

Chapter 1: PCI Needed Improvement

Wait States Yield Poor Performance

Relatively Slow Clock Speed

Transfer Size Unknown

PCI Delayed Transactions Are Inefficient

Snoops Hurt Performance

Processor(s)

Latency Timer Use Not Optimized in PCI

Data Phase Parity Error Recovery Usually Not Possible

No Indication of Device Width

MSI Feature Optional in PCI Environment

Power Management Optional

Configuration Software Constrained by 32-Bit Memory BARs

Stepping Yields Poor Performance

Chapter 2: PCI-X Improves on PCI

PCI-X Is Backward-Compatible With PCI

PCI-X Is More System-Centric Than PCI

Higher Clock Speeds Possible

Wait States Eliminated

Data Transferred in Blocks

Disconnecting on Block Boundaries

Latency Timer Usage

Requester and Completer

Transfer Size Specified

Requester ID and Transaction ID Are Specified

Split Transactions Replace Delayed Transactions

Dynamic Traffic Analysis and Load Tuning

Data Phase Parity Error Recovery

64-Bit Connection Indication

MSI Feature Mandatory

Power Management Mandatory for Add-In Devices

Snoops Can Be Eliminated

Memory BARS Must Be 64-Bit Width

Bus Masters That Access Memory Must Support DAC Command

Stepping Eliminated

Fast Back-to-Back Transactions Eliminated

Chapter 3: Lowest Common Denominator Defines Mode

Bus Protocol/Speed = Lowest Common Denominator

Discovering a PCI-X Bus

Discovering PCI Devices on a PCLX Bus

Some Example Systems

Systems Supporting Both PCI-X and PCI Environments

Chapter 4: Device Types and Bus Initialization

All Devices Support 33MHz PCI

All PCI-X Devices Support 66MHz PCI-X Mode

PCIXCAP Indicates Protocol/Frequency Required

Device Not Permitted to Use PCIXCAP as Input or Output

Bridge's Interpretation of M66EN and PCIXCAP

Maximum Reliable Speed Verified by Design and Testing

Supplying PCI-X Devices With Protocol and Speed

Why Bus Must Be Idle When Init Pattern Driven

Upon Receipt of Pattern. Device Initializes Itself

Init Pattern Setup and Hold Time

Reassertion of RST# Necessitates Redelivery of Pattern

Bridge Must Support Interfaces in Different Modes

Hot-Plug PCI-X Bus Initialization

Placing Device in Low-Power Mode Requires Quiesce

Chapter 5: PCI-X Is a Registered Bus

PCI-X Is a Low-Voltage Swing (LVS) Bus

Introduction to the Registered Nature of the Bus

Address/Command Decode Example

Data Read Example

Chapter 6: Intro to Commands

Commands Fall Into Three Categories

Command Encoding

Dword Commands

Burst Commands

Dual-Address Cycle (DAC) Command

Chapter 7: Intro to Transaction Phases

The PCI Transaction Phases

The PCLX Transaction Phases

Chapter 8: Intro to Transaction Termination

Introduction

Initiator Termination of Transaction

Early Target Termination of Transaction

Bridge Handling of Memory Writes

Bridge Handling of Transactions Other Than Memory Writes

Chapter 9: Intro to Split and Immediate Transactions

Definition of Requester and Completer

Definition of a Sequence

Definition of Requester ID, Tag, and Sequence ID

How Does a Device Know Its Requester ID?

Immediate Transaction

Memory Writes Are Posted

Split Transactions

Part 2: Transaction Protocol

Chapter 10: Bus Arbitration

Stepping Not Permitted

Request and Grant Signals Are Registered

Example Arbitration

Device Design Rules

Arbiter Design Rules

Bus Parking

How the Initiator Deals With Preemption

Chapter 11: Detailed Command Description

Dword Commands,

Burst Commands

Dual-Address Cycle (DAC) Command

Chapter 12: Latency Rules

Initiator Latency Rules

Target Latency Rules

Maximum Completion Time

Chapter 13: The Address. Attribute and Response Phases

All Transactions Begin With Address and Attribute Phases

Memory Transaction May Have Two Address Phases

Attributes Always Delivered on Lower Half of Bus

Address/Attribute Format Depends on Command Type

Memory Burst Format

Dword Command (other than Config) Format

Configuration Command Format

Split Completion Command Format

The Response Phase: Connecting With the Target

Chapter 14: Dword Transactions

General

General Format of Timing Diagram Descriptions

IO Read and Memory Read Dword

IO Write

Configuration Read and Write Transactions

Interrupt Acknowledge Command

Special Cycle Command

Chapter 15: Burst Transactions

Introduction

General Format of Timing Diagram Descriptions

Memory Read Block Transaction

Memory Write Block Transaction

Memory Write Transaction

Split Completion Transaction

Alias To Memory Block Commands

Chapter 16: Transaction Terminations

General Format of Timing Diagram Descriptions

Termination by the Initiator

Termination By the Target

Chapter 17: Split Completion Messages

Purpose of Split Completion Messages

SCM Always Terminates a Sequence

Upon Receipt of Error Message, Set Status Bit

Message Format

Write Completion Indication

Read Completion Indication

Device-Specific Error Handling

Chapter 18: 64-Bit Transactions

General Format of Timing Diagram Descriptions

64-Bit Data Transfers and 64-Bit Addressing: Separate Capabilities

64-Bit Extension Signals

REQ64# and ACK64# Have Same Timing as FRAME# and DEVSEL#

In Attribute Phase, Upper Bus Reserved and Driven High

Block Length Remains the Same

Bursts Cannot Cross 264 Boundary

REQ64# Not Permitted in Dword Transactions

MSI Write Always Writes a Single 32-Bit Data Value

Bridge Must Support DAC on Both Interfaces

Width of Function's Connection to Bus

64-Bit Cards in 32-Bit Add-In Connectors

Pullups Prevent 64-Bit Extension From Floating When Not in Use

64-Bit Data Transfer Capability

Addressing Memory Above 4GB Boundary

Add-In Card Trace Length

Parity Generation and Checking

Chapter 19: Parity Generation and Checking

General Discussion of Parity Generation

General Discussion of Parity Checking

In Any Phase, Agent Driving AD Bus Supplies Parity

As in PCI, Even Parity Is Used

No Parity in Response Phase

Address Phase Parity

Attribute Phase Parity

Data Phase Parity

Part 3: Device Configuration

Chapter 20: Configuration Transactions

Configuration Software Mechanism Same as PCI

Configuration Transactions Can Only Flow Downstream

Special Cycle Request Can Flow Upstream or Downstream

Type 0: Access Registers in Function on This Bus

Type 1: Access Registers in Function on Bus Farther Out in Hierarchy

Type 0 Configuration Transactions

Type 1 Configuration Transactions

Arbiter's Treatment of Configuration Access

Generation of Special Cycle Under Software Control

Chapter 21: Non-Bridge Configuration Registers

Detecting a PCI-X Capable Bridge

Detecting Capabilities of Functions on Bus

Most PCI Configuration Registers Remain Unchanged

Some PCI Con fig Registers Affected by Protocol Mode

Function's PCI-X Capability Register Set

Chapter 22: Bridge Configuration Registers

Discovering a PCIX-to-PCIX Bridge

Many Bridge PCI Configuration Registers Unchanged

Some Bridge PCI Configuration Registers Affected by Mode

Bridge's PCLX Capability Register Set

Optional Bridge Registers

Part 4: Load Tuning

Chapter 23: Load Tuning Mechanisms

Introduction to Load Tuning

Non-Bridge Function Tuning

Bridge Tuning

Part 5: PCI-X Bridges

Chapter 24: PCIX-to-PCIX Bridges

Performs Same Function as a PCI-to-PCI Bridge

Support for DAC Command

Bus Width

Memory Writes Crossing Bridge Are Always Posted

Other Transactions Crossing Bridge Are Always Split

How the Bridge Claims Split Completions

When Bridge Can Use Retry or Disconnect At Next ADB

Interfaces Can Be in Different Modes/Speeds

Translating PCI to PCI-X

Translating PCI-X to PCI

Error Handling

Buffer Size

When a Request Is Bigger Than the Bridge Buffer

Application Bridge

Bridge Acceptance Rules

Ordering and Passing Rules

Decomposing Split Transactions (sounds morbid!)

Chapter 25: Locked Transaction Series

Definition of Downstream and Upstream

Basics

Only Host/PCIX Bridge Originates Downstream Locked Series

PCI-X Bridges Only Pass Locked Series Downstream

Only EISA Bridge Originates Upstream Locked Traffic

Application Bridge May or May Not Support Locking

EISA Bridge Supports LOCK# As Input, Not as Output

Non-Bridge Devices Ignore LOCK#

Sequence of Events

Split Completion Error Message Terminates Lock

Upstream Bridge (Initiating Bridge) Rules

Downstream Bridge (Target Bridge) Rules

Arbitration

Starting Locked Transaction Series

Continuing Locked Transaction Series

Attempted Access to Bridge by Device Other Than Owner

Last Transaction in Locked Series

When Bridge Starts Second Series Immediately After First

Retry Issued to Owner Not a Problem

DAC Command Lock Timing

Part 6: Error Detection and Handling

Chapter 26: Error Detection and Handling

Handling of a Target Abort

Handling of a Master Abort

Target Handling of Address or Attribute Phase Parity Error

Data Phase Parity

Split Read Errors

Requester Handling of Unexpected Split Completion