传感器和通信中的CMOS级联式Sigma-Delta调制器

传感器和通信中的CMOS级联式Sigma-Delta调制器
作 者: 麦迪瑞
出版社: 科学出版社
丛编项: 国外电子信息精品著作
版权说明: 本书为出版图书,暂不支持在线阅读,请支持正版图书
标 签: 场效应型
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作者简介

暂缺《传感器和通信中的CMOS级联式Sigma-Delta调制器》作者简介

内容简介

CMOS级联式Sigma-Delta调节器是近年来研究的热点,作为一种较新的结构形式,国内外都比较重视。尤其是对于ADC的研究,作为数模混合CMOS电路的研究典型,在国内非常热。《传感器和通信中的CMOS级联式Sigma-Delta调制器(影印版)》对sigma-delta调制器作了全面的分析,深入探讨了其在传感器接口和无线通信中的应用。对误差分析、级连结构、电路、模型,以及实际设计重点考虑的内容,都进行了全面的阐述。《传感器和通信中的CMOS级联式Sigma-Delta调制器(影印版)》与其他同类书不同之处在于其完整、深入地对开关电容电路的误差进行了详细分析。《传感器和通信中的CMOS级联式Sigma-Delta调制器(影印版)》内容全面、由浅入深、适用面广、适合相关专业的高级科技工作者和研究生参考,对高年级本科生也具有参考价值。

图书目录

Preface

List of Abbreviations

CHAPTER 1 ∑△ ADCs: Principles, Architectures, and State of the Art

1.1. Analog-to-Digital Conversion: Fundamentals

1.1.1. Sampling

1.1.2. Quantization

1.2. Oversampling ∑△ ADCs: Fundamentals

1.2.1. Oversampling

1.2.2. Noise-shaping

1.2.3. Basic architecture of oversampling ZA ADCs

1.2.4. Performance metrics

1.2.5. Ideal performance

1.3. Single-Loop ∑△ Architectures

1.3.1. 1st-order ∑△ modulator

1.3.2. 2nd-order ∑△ modulator

1.3.3. High-order ∑△ modulators

Stability concerns

Optimized NTFs

High-order topologies

Non-linear stabilization techniques

1.4. Cascade ∑△ Architectures

1.5. Multi-Bit ∑△ Architectures

Influence of DAC errors

1.5.1. Element trimming and analog calibration

1.5.2. Digital correction

1.5.3. Dynamic element matching

1.5.4. Dual-quantization

Leslie-Singh architecture

Single-loop ∑△Ms

Cascade ∑△Ms

1.6. Parallel ∑△ Architectures

1.6.1. Frequency division multiplexing

1.6.2. Time division multiplexing

1.6.3. Code division multiplexing

1.7. State of the Art in ∑△ ADCs

1.8. Summary

CHAPTER 2 Non-ldeal Performance of ∑△ Modulators

2.1. Integrator Leakage

Leaky integrator

2.1.1. Single-loop ∑△ modulators

1st-order loop

2nd-order loop

Lth-order loops

2.1.2. Cascade ∑△ modulators

2.2. Capacitor Mismatch

2.2.1. Single-loop ∑△ modulators

2nd-order loop

Lth-order loops

2.2.2. Cascade ∑△ modulators

2.3. Integrator Settling Error

2.3.1. Model for the transient response of SC integrators

SC integrator model

Transient during integration

Transient during sampling

Integration-sampling process

2.3.2, Validation of the proposed model

Comparison with experimental results

Comparison with traditional models

2.3.3. Effect of the amplifier finite gain-bandwidth product

Single-loop ∑△ modulators

Cascade ∑△ modulators

2.3.4. Effect of the amplifier finite slew rate

2.3.5. Effect of the switch finite on-resistance

Effect on an ideal integrator

Effect on the amplifier GB

Effect on the amplifier SR

2.4. Circuit Noise

2.4.1. Noise in track-and-holds

Track component

……

CHAPTER 3 A Wideband ZA Modulator in 3.3-V 0.35-um CMOS

CHAPTER 4 A∑△Modulator in 2.5-V 0.25-um CMOS for ADSUADSL+

CHAPTER 5 A∑△Modulator with Programmable Signal Gain for Automotive Sensor Inte~aces

APPENDIX A An Expandible Family of Cascade∑△Modulators

APPENDIX B Power Estimator for Cascade∑△Modulators

REFERENCES

Index